HM51W16165 Series, HM51W18165 Series
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS.
22. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the later rising edge of UCAS or LCAS.
23. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS.
24. tCP is determined by the time that both UCAS and LCAS are high.
25. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater
than the specified tHPC (min) value.The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
26. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF
.
28. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS
precharge time should use tRPS instead of tRP.
29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024
cycles (4096 cycles: HM51W16165 Series, 1024 cycles: HM51W18165 Series) of distributed
CBR refresh with 15.6 µs interval should be executed within 64 or 16 ms (64 ms: HM51W16165,
16 ms: HM51W18165) immediately after exiting from and before entering into the self refresh
mode.
31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
32. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
Data Sheet E0153H10
16
ELPIDA [ ELPIDA MEMORY ]
