EDS2532EGBH-TT
DC Characteristics 1 (TA = –20°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
IDD1
Grade
max.
Unit
mA
Test condition
Notes
1, 2, 3
Burst length = 1
-6D
-7B
50
50
Operating current
tRC = tRC (min.)
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
CKE ≤ 0.3V,
Standby current in power down
IDD2P
0.8
0.6
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
tCK = tCK (min.)
6
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
CKE ≤ 0.3V, tCK = ∞
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
Standby current in power down
(input signal stable)
IDD2PS
IDD2N
IDD2NS
IDD3P
7
CKE, /CS = VIH,
Standby current in non power down
tCK = tCK (min.)
4
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
Standby current in non power down
(input signal stable)
CKE = VIH, tCK = ∞,
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
4.0
4.0
3.0
15
8
CKE ≤ VIL,
Active standby current in power down
tCK = tCK (min.)
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
Active standby current in power down
(input signal stable)
CKE ≤ VIL, tCK = ∞
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
IDD3PS
CKE, /CS = VIH,
Active standby current in non power down IDD3N
tCK = tCK (min.)
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
Active standby current in non power down
IDD3NS
CKE = VIH, tCK = ∞,
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
10
(input signal stable)
tCK = tCK (min.),
-6D
-7B
85
70
Burst operating current
IDD4
BL = 4
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
-6D
-7B
110
100
3.0
tRC = tRC (min.)
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
Refresh current
IDD5
IDD6
mA
mA
Self-refresh current
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E1200E40 (Ver. 4.0)
5
ELPIDA [ ELPIDA MEMORY ]
