EDS2532EGBH-TT
Test Conditions
• Input and output timing reference levels: VDDQ × 0.5
• Input waveform and output load: See following figures
1.6V
I/O
1.4V
input
0.3V
0.2V
CL
t
T
tT
Output load
Relationship Between Frequency and Minimum Latency
Number of clock cycle
Parameter
tCK (ns)
Symbol
6
3
7.5
3
Unit
tCK
Notes
1
Active command to column command
(same bank)
lRCD
Active command to active command
lRC
10
7
9
6
3
2
tCK
tCK
tCK
tCK
1
1
1
1
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge command
(same bank)
lRAS
lRP
3
lDPL
3
Active command to active command
lRRD
lSREX
lDAL
2
1
6
2
1
5
tCK
tCK
tCK
1
2
(different bank)
Self-refresh exit time
Last data in to active command
(Auto precharge, same bank)
= [lRC]
3
Self-refresh exit to command input
lSEC
lHZP
lAPR
11
3
9
3
1
tCK
tCK
tCK
Precharge command to high impedance
Last data out to active command
(Auto precharge, same bank)
1
Last data out to precharge (early precharge)
Column command to column command
Write command to data in latency
DQM to data in
lEP
–2
1
–2
1
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
lCCD
lWCD
lDID
0
0
0
0
DQM to data out
lDOD
lCLE
lMRD
lCDD
lPEC
2
2
CKE to CLK disable
1
1
Mode register set to active command
/CS to command disable
2
2
0
0
Power down exit to command input
1
1
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of Self-refresh exit.
3. Except [DESL] and [NOP]
Preliminary Data Sheet E1200E40 (Ver. 4.0)
8
ELPIDA [ ELPIDA MEMORY ]
