EDS2532EGBH-TT
AC Characteristics (TA = –20°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
-6D
min.
6
-7B
min.
7.5
2.5
2.5
—
Parameter
Symbol
tCK
tCH
tCL
max.
—
max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
System clock cycle time
CLK high pulse width
2.5
2.5
—
—
—
1, 5
CLK low pulse width
—
—
1, 5
Access time from CLK
Data-out hold time
tAC
tOH
tLZ
5.4
—
5.4
—
1, 2, 5
1, 2, 5
1, 2, 3, 5
1, 4
2.5
0
2.5
0
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
—
—
tHZ
—
5.4
—
—
5.4
—
tSI
1.5
0.8
60
42
1.5
0.8
66
1, 5
Input hold time
tHI
—
—
1, 5
Ref/Active to Ref/Active command period
tRC
tRAS
—
—
1
Active to Precharge command period
120000
42
120000
1
Active command to column command
(same bank)
Precharge to active command period
Write recovery or data-in to precharge
lead time
tRCD
tRP
18
18
15
—
—
—
22.5
22.5
15
—
—
—
ns
ns
ns
1
1
1
tDPL
2CLK +
tRP
2CLK +
tRP
Last data into active latency
tDAL
—
—
Active (a) to Active (b) command period
Transition time (rise and fall)
tRRD
tT
12
—
15
—
ns
ns
1
0.5
1.0
0.5
1.0
Refresh period
(4096 refresh cycles)
tREF
—
64
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 0.5 × VDDQ.
2. Access time is measured at 0.5 × VDDQ. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
5. If tT ≥ 1ns, each parameters is changed as follows;
tAC, tOH, tLZ: should be added (tT (rise)/2 – 0.5)
tCH, tCL, tSI, tHI: should be added {(tT (rise) + tT (fall))/2 – 1}
Preliminary Data Sheet E1200E40 (Ver. 4.0)
7
ELPIDA [ ELPIDA MEMORY ]
