EDJ1108BABG, EDJ1116BABG
IDD Measurement Conditions for IDD3N, IDD3P (fast exit)
Symbol
IDD3N
IDD3P (1)
Active power-down current*
(always fast exit)
Name
Active standby current
Measurement Condition
Timing Diagram Example
Figure IDD2N/IDD3N Example
CKE
H
L
External Clock
tCK
on
on
tCK min (IDD)
tCK min (IDD)
N/A
tRC
N/A
N/A
N/A
N/A
N/A
N/A
H
tRAS
tRCD
tRRD
CL
N/A
N/A
N/A
N/A
AL
N/A
/CS
STABLE
SWITCHIN
Address and command inputs
STABLE
FLOATING
off / 1
(see Definition of SWITCHING table)
SWITCHING
(see Definition of SWITCHING table)
Data inputs
Output buffer DQ, DQS
/ MR1 bit A12
off / 1
disabled
/ [0,0,0]
/ [0,0]
disabled
/ [0,0,0]
/ [0,0]
ODT
/ MR1 bits [A9, A6, A2]
/ MR2 bits [A1, A0]
Burst length
Active banks
Idle banks
N/A
N/A
all
all
none
none
Precharge Power-down
Mode / MR0 bit A12
N/A (Active Power-down
Mode is always “Fast Exit” with DLL-on)
N/A
Note: DDR3 will offer only one active power-down mode with DLL-on (-> fast exit). MR0 bit A12 will not be used for
active power-down. Instead bit A12 will be used to switch between two different precharge power-down
modes.
Data Sheet E1248E40 (Ver. 4.0)
37
ELPIDA [ ELPIDA MEMORY ]
