EDJ1108BABG, EDJ1116BABG
The following conditions apply:
• IDD specifications are tested after the device is properly initialized.
• Input slew rate is specified by AC Parametric test conditions.
• IDD parameters are specified with ODT and output buffer disabled (MR1 bit A12 = 1).
IDD Measurement Conditions for IDD0 and IDD1
Symbol
Name
IDD0
IDD1
Operating Current 1
-> One Bank Activate
-> Read
Operating Current 0
-> One Bank Activate
-> Precharge
-> Precharge
Measurement Condition
Timing Diagram Example
Figure IDD1 Example
CKE
H
H
External Clock
tCK
on
on
tCK min (IDD)
tRC min (IDD)
tRAS min (IDD)
N/A
tCK min (IDD)
tRC min (IDD)
tRAS min (IDD)
tRCD min (IDD)
N/A
tRC
tRAS
tRCD
tRRD
CL
N/A
N/A
CL(IDD)
AL
N/A
0
/CS
H between. Activate and Precharge Commands H between Activate, Read and Precharge
SWITCHING (see Definition of SWITCHING
table); only exceptions are Activate and
SWITCHING (see Definition of SWITCHING
table); only exceptions are Activate, Read and
Precharge commands; example of IDD0 pattern: Precharge commands; example of IDD1 pattern:
A0 D /D /D D D /D /D D D /D/D D D /D P0
A0 D /D /D D R0 /D /D D D /D/D D D /D P0
Command inputs
(/CS, /RAS, /CAS, /WE)
(DDR3-800: tRAS = 37.5ns between (A)ctivate (DDR3-800 -555: tRCD = 12.5ns between
and (P)recharge to bank 0;
(A)ctivate and (R)ead to bank 0;
Definition of D and /D: see Definition of
SWITCHING table
Definition of D and /D: see Definition of
SWITCHING table
Row addresses SWITCHING (see Definition of Row addresses SWITCHING (see Definition of
Row, column addresses
Bank addresses
SWITCHING table); A10 must be L all the time! SWITCHING table);A10 must be L all the time!
Bank address is fixed (bank 0)
Bank address is fixed (bank 0)
Read Data: output data switches every clock,
which means that Read data is stable during one
clock cycle.
To achieve IOUT = 0mA the output buffer should
be switched off by MR1 bit A12 set to “1”.
When there is no read data burst from DRAM the
DQ I/O should be FLOATING.
SWITCHING (see Definition of SWITCHING
table)
Data I/O
Output Buffer DQ, DQS
/ MR1 bit A12
off / 1
off / 1
disabled
/ [0,0,0]
/ [0,0]
disabled
/ [0,0,0]
/ [0,0]
ODT
/ MR1 bits [A9, A6, A2]
/ MR2 bits [A1, A0]
Burst length
Active banks
Idle banks
N/A
one
ACT-PRE loop
all other
8 fixed / MR0 bits [A1, A0] = {0,0}
one
ACT-READ-PRE loop
all other
Precharge Power-down
Mode / MR0 bit A12
N/A
N/A
Data Sheet E1248E40 (Ver. 4.0)
33
ELPIDA [ ELPIDA MEMORY ]
