EDJ1108BABG, EDJ1116BABG
IDD Measurement Conditions for IDD2N, IDD2P (1), IDD2P (0) and IDD2Q
Symbol
IDD2N
IDD2P (1)*1
IDD2P (0)*1
IDD2Q
Precharge power-down Precharge power-down
current
current
Precharge standby
current
Precharge quiet
standby current
Name
(fast exit
(slow exit
MR0 bit A12= 0)
MR0 bit A12= 1)
Measurement Condition
Timing Diagram Example
Figure IDD2N/IDD3N
Example
CKE
H
L
L
H
External Clock
tCK
on
on
on
on
tCK min (IDD)
tCK min (IDD)
N/A
tCK min (IDD)
N/A
tCK min (IDD)
tRC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
tRAS
tRCD
tRRD
CL
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AL
N/A
N/A
/CS
H
STABLE
STABLE
Bank address,
row address and command
inputs
SWITCHING (see
Definition of SWITCHING STABLE
table)
STABLE
STABLE
Data inputs
Output buffer DQ, DQS
/ MR1 bit A12
SWITCHING
FLOATING
FLOATING
off / 1
FLOATING
off / 1
off / 1
off / 1
disabled
/ [0,0,0]
/ [0,0]
disabled
/ [0,0,0]
/ [0,0]
disabled
/ [0,0,0]
/ [0,0]
disabled
/ [0,0,0]
/ [0,0]
ODT
/ MR1 bits [A9, A6, A2]
/ MR2 bits [A1, A0]
Burst length
Active banks
Idle banks
N/A
none
all
N/A
none
all
N/A
none
all
N/A
none
all
Slow exit / 0
Fast exit / 1
Slow exit
Precharge Power-down
Mode / MR0 bit A12
N/A
N/A
(any valid command
(READ and ODT
commands must satisfy
tXPDLL-AL)
after tXP*2)
Notes: 1. In DDR3 the MR0 bit A12 defines DLL-on/off behaviors only for precharge power-down. There are two
different precharge power-down states possible: one with DLL-on (fast exit, bit A12 = 1) and one with
DLL-off (slow exit, bit A12 = 0).
2. Because it is an exit after precharge power-down the valid commands are: bank activate (ACT), auto-
refresh (REF), mode register set (MRS), self-refresh (SELF).
Data Sheet E1248E40 (Ver. 4.0)
35
ELPIDA [ ELPIDA MEMORY ]
