EDJ1108BABG, EDJ1116BABG
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12
T13
T14 T15 T16
T17
T18
CK
/CK
BA 0 to 2
0
Address
3FF
000
000
3FF
0 0 0
3FF
11
(A0 to A9)
Address
(A10)
L
Address
(A11 to A12)
11
00
00
00
0 0
/CS
/RAS
/CAS
/WE
Command
DQ
ACT
D
/D
/D
D
READ
/D
/D
D
D
/D
0
/D
1
D
0
D
/D
PRE
D
D
/D
/D
0
1
0
1
1
IDD1 measurement loop
DM
IDD1 Example* (DDR3-800-555, 512Mb ×8)
Note: Data DQ is shown but the output buffer should be switched off (per MR1 bit A12 = 1) to achieve IOUT = 0mA.
Address inputs are split into 3 parts.
Data Sheet E1248E40 (Ver. 4.0)
34