EDJ1108BABG, EDJ1116BABG
IDD Measurement Conditions for IDD4R, IDD4W and IDD7
Symbol
IDD4R
IDD4W
IDD7
Operating current
(Burst read operating)
Operating current
(Burst write operating)
Name
All bank interleave read current
Measurement Condition
Timing Diagram Example
IDD4R Example
CKE
H
H
H
External Clock
tCK
on
on
on
tCK min (IDD)
tCK min (IDD)
tCK min (IDD)
tRC min. (IDD)
tRAS min. (IDD)
tRCD min. (IDD)
tRRD min. (IDD)
CL (IDD)
tRC
N/A
N/A
tRAS
tRCD
tRRD
CL
N/A
N/A
N/A
N/A
N/A
N/A
CL (IDD)
CL (IDD)
AL
0
0
tRCD min. − 1tCK
H between valid commands
/CS
H between valid commands
H between valid commands
SWITCHING (see Definition of
SWITCHING table);
SWITCHING (see Definition of
SWITCHING table);
only exceptions are read
commands -> IDD4R pattern:
only exceptions are write
commands -> IDD4W pattern:
Command inputs
(/CS, /RAS, /CAS, /WE)
For patterns see pattern in IDD7
Timing Patterns section
R0 D /D /D R1 D /D /D R2 D /D W0 D /D /D W1 D /D /D W2 D /D
/D R3 D /D /D R4 .....
/D W3 D /D /D W4...
Rx = Read from bank x;
Definition of D and /D: see
Wx = Write to bank x;
Definition of D and /D: see
Definition of SWITCHING table Definition of SWITCHING table
Column addresses SWITCHING Column addresses SWITCHING
(see Definition of SWITCHING
table);
A10 must be L all the time!
(see Definition of SWITCHING
table);
A10 must be L all the time!
Row, column addresses
Bank addresses
STABLE during DESELECTs
bank address cycling
(0 -> 1 -> 2 -> 3 ...), see pattern
in IDD7 Timing Patterns section
bank address cycling
(0 -> 1 -> 2 -> 3 ...)
bank address cycling
(0 -> 1 -> 2 -> 3 ...)
Seamless read data burst (BL8):
output data switches every
clock, which means that Read
data is stable during one clock
cycle.
Read data (BL8): output data
Seamless write data burst (BL8): switches every clock, which
input data switches every clock, means that Read data is stable
which means that write data is
stable during one clock cycle.
during one clock cycle.
Data I/O
To achieve IOUT = 0mA the
output buffer should be switched
off by MR1 bit A12 set to “1”.
To achieve IOUT = 0mA the
output buffer should be switched
off by MR1 bit A12 set to “1”.
DM is low all the time
Output Buffer DQ, DQS
/ MR1 bit A12
off / 1
off / 1
off / 1
disabled
/ [0,0,0]
/ [0,0]
disabled
/ [0,0,0]
/ [0,0]
disabled
/ [0,0,0]
/ [0,0]
ODT
/ MR1 bits [A9, A6, A2]
/ MR2 bits [A1, A0]
8 fixed / MR0 bits [A1, A0] =
{0,0}
8 fixed / MR0 bits [A1, A0] =
{0,0}
Burst length
8 fixed / MR0 [A1, A0] = {0,0}
Active banks
Idle banks
all
all
all, rotational
none
none
none
Precharge Power-down
Mode / MR0 bit A12
N/A
N/A
N/A
Data Sheet E1248E40 (Ver. 4.0)
38
ELPIDA [ ELPIDA MEMORY ]
