EDJ1108BABG, EDJ1116BABG
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12
CK
/CK
BA
1
2
3
0
0 to 2
Address
(A0 to A9)
3FF
000
3FF
0 0 0
Address
(A10)
L
Address
(A11 to A12)
11
00
11
0 0
/CS
/RAS
/CAS
/WE
Command
0 to 2
READ
D
/D
/D
READ
D
/D
/D
READ
D
/D
/D
READ
D
DQ
00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF
0 to 7
Start of measurement loop
DM
IDD4R Example* (DDR3-800-555, 512Mb ×8)
Note: Data DQ is shown but the output buffer should be switched off (per MR1 bit A12 = 1) to achieve IOUT = 0mA.
Address inputs are split into 3 parts.
Data Sheet E1248E40 (Ver. 4.0)
39