EDD51323DBH-LS
-5BLS
min.
-6ELS
min.
Parameter
Symbol
tDAL
max.
—
max.
—
Unit
Notes
9
Autoprecharge write recovery and
precharge time
—
—
Self-refresh exit period
tSREX
120
2
—
120
1
—
ns
Internal Write to Read command delay tWTR
Average periodic refresh interval tREF
—
—
tCK
µs
—
7.8
—
7.8
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver
strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VDDQ/2.
3. The timing reference level is VDDQ/2.
4. Output valid window is defined to be the period between two successive transition of data out signals.
The signal transition is defined to occur when the signal level crossing VDDQ/2.
5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
8. tAC, tDQSCK, tHZ and tLZ are specified with 15pF bus loading condition.
9. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and
minimum 1 clock for tRP.
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next
higher integer.
Preliminary Data Sheet E1432E20 (Ver. 2.0)
9
ELPIDA [ ELPIDA MEMORY ]
