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EDD51323DBH-6ELS-F 参数 Datasheet PDF下载

EDD51323DBH-6ELS-F图片预览
型号: EDD51323DBH-6ELS-F
PDF下载: 下载PDF文件 查看货源
内容描述: 512M DDR位移动RAM ™ WTR (宽温度范围) ,低功耗功能 [512M bits DDR Mobile RAM™ WTR (Wide Temperature Range), Low Power Function]
分类和应用: 双倍数据速率
文件页数/大小: 60 页 / 761 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDD51323DBH-LS  
-5BLS  
min.  
-6ELS  
min.  
Parameter  
Symbol  
tDAL  
max.  
max.  
Unit  
Notes  
9
Autoprecharge write recovery and  
precharge time  
Self-refresh exit period  
tSREX  
120  
2
120  
1
ns  
Internal Write to Read command delay tWTR  
Average periodic refresh interval tREF  
tCK  
µs  
7.8  
7.8  
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver  
strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.  
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal  
transition is defined to occur when the signal level crossing VDDQ/2.  
3. The timing reference level is VDDQ/2.  
4. Output valid window is defined to be the period between two successive transition of data out signals.  
The signal transition is defined to occur when the signal level crossing VDDQ/2.  
5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The  
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage  
level, but specify when the device output stops driving.  
6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This  
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins  
driving.  
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific  
reference voltage to judge this transition is not given.  
8. tAC, tDQSCK, tHZ and tLZ are specified with 15pF bus loading condition.  
9. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and  
minimum 1 clock for tRP.  
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next  
higher integer.  
Preliminary Data Sheet E1432E20 (Ver. 2.0)  
9