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EDD51323DBH-6ELS-F 参数 Datasheet PDF下载

EDD51323DBH-6ELS-F图片预览
型号: EDD51323DBH-6ELS-F
PDF下载: 下载PDF文件 查看货源
内容描述: 512M DDR位移动RAM ™ WTR (宽温度范围) ,低功耗功能 [512M bits DDR Mobile RAM™ WTR (Wide Temperature Range), Low Power Function]
分类和应用: 双倍数据速率
文件页数/大小: 60 页 / 761 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDD51323DBH-6ELS-F的Datasheet PDF文件第4页浏览型号EDD51323DBH-6ELS-F的Datasheet PDF文件第5页浏览型号EDD51323DBH-6ELS-F的Datasheet PDF文件第6页浏览型号EDD51323DBH-6ELS-F的Datasheet PDF文件第7页浏览型号EDD51323DBH-6ELS-F的Datasheet PDF文件第9页浏览型号EDD51323DBH-6ELS-F的Datasheet PDF文件第10页浏览型号EDD51323DBH-6ELS-F的Datasheet PDF文件第11页浏览型号EDD51323DBH-6ELS-F的Datasheet PDF文件第12页  
EDD51323DBH-LS  
AC Characteristics  
(TA = 25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)  
-5BLS  
min.  
5.0  
-6ELS  
min.  
6.0  
Parameter  
Symbol  
tCK  
max.  
max.  
Unit  
ns  
Notes  
Clock cycle time  
CK high-level width  
CK low-level width  
tCH  
0.45  
0.55  
0.55  
0.45  
0.55  
0.55  
tCK  
tCK  
tCL  
0.45  
0.45  
min.  
( tCH, tCL)  
min.  
( tCH, tCL)  
CK half period  
tHP  
tCK  
DQ output access time from CK, /CK  
DQS-in cycle time  
tAC  
2.0  
0.9  
2.0  
5.0  
1.1  
5.0  
2.0  
0.9  
2.0  
5.0  
1.1  
5.0  
ns  
2, 8  
tDSC  
tCK  
ns  
DQS output access time from CK, /CK tDQSCK  
DQ-out high-impedance time from CK,  
/CK  
DQ-out low-impedance time from CK,  
/CK  
2, 8  
5, 8  
tHZ  
5.0  
5.0  
ns  
ns  
tLZ  
1.0  
1.0  
6, 8  
DQS to DQ skew  
tDQSQ  
tQH  
0.4  
0.5  
ns  
3
4
DQ/DQS output hold time from DQS  
Data hold skew factor  
DQ and DM input setup time  
DQ and DM input hold time  
DQ and DM input pulse width  
Read preamble  
tHP tQHS  
tHP tQHS  
ns  
tQHS  
0.5  
0.65  
ns  
tDS  
0.48  
0.48  
1.6  
0.9  
0.4  
0
0.6  
0.6  
1.6  
0.9  
0.4  
0
ns  
3
3
tDH  
ns  
tDIPW  
tRPRE  
tRPST  
tWPRES  
tWPRE  
tWPST  
ns  
1.1  
0.6  
1.1  
0.6  
tCK  
tCK  
ns  
Read postamble  
Write preamble setup time  
Write preamble  
0.25  
0.4  
0.25  
0.4  
tCK  
tCK  
Write postamble  
0.6  
0.6  
7
Write command to first DQS latching  
transition  
tDQSS  
0.75  
1.25  
0.75  
1.25  
tCK  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
DQS input high pulse width  
tDSS  
tDSH  
tDQSH  
tDQSL  
tIS  
0.2  
0.2  
0.40  
0.40  
0.9  
0.9  
2.3  
2
0.2  
0.2  
0.40  
0.40  
1.1  
1.1  
2.7  
2
tCK  
tCK  
tCK  
tCK  
ns  
DQS input low pulse width  
Address and control input setup time  
Address and control input hold time  
Address and control input pulse width  
3
3
3
tIH  
ns  
tIPW  
ns  
Mode register set command cycle time tMRD  
tCK  
ns  
Active to Precharge command period  
tRAS  
40  
120000  
42  
120000  
Active to Active/Auto-refresh command  
tRC  
55  
72  
60  
72  
ns  
ns  
period  
Auto-refresh to Active/Auto-refresh  
command period  
tRFC  
Active to Read/Write delay  
tRCD  
tRP  
15  
15  
18  
18  
ns  
ns  
Precharge to active command period  
Column address to column address  
delay  
tCCD  
1
1
tCK  
Active to active command period  
tRRD  
tWR  
10  
15  
12  
15  
ns  
ns  
Write recovery time  
Preliminary Data Sheet E1432E20 (Ver. 2.0)  
8