EDD51323DBH-LS
Timing Parameter Measured in Clock Cycle
Number of clock cycle
5.0ns
tCK
6.0ns
min.
7.5ns
Parameter
Symbol
tWPD
min.
max.
max.
min.
max.
Unit
tCK
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
4 + BL/2
4 + BL/2
BL/2
3 + BL/2
tRPD
BL/2
BL/2
tCK
tCK
Write to read command delay
(to input all data)
tWRD
3 + BL/2
2 + BL/2
2 + BL/2
Burst stop command to write
command delay
tBSTW
tBSTZ
tRWD
tHZP
3
3
3
tCK
tCK
tCK
tCK
(CL = 3)
Burst stop command to DQ high-Z
(CL = 3)
Read command to write command
delay (to output all data)
(CL = 3)
Pre-charge command to high-Z
(CL = 3)
3
3
3
3 + BL/2
3
3 + BL/2
3
3 + BL/2
3
Write command to data in latency
Write recovery
tWCD
tWR
1
3
0
1
3
0
1
2
0
tCK
tCK
tCK
DM to data in latency
tDMD
Mode register set command cycle
tMRD
2
2
2
tCK
tCK
time
Self-refresh exit to non-column
command
tSREX
24
20
16
Auto-refresh period
tRFC
15
2
12
2
10
1
tCK
tCK
tCK
tCK
Power-down entry
tPDEN
tPDEX
tCKE
Power-down exit to command input
CKE minimum pulse width
1
1
1
2
2
2
Preliminary Data Sheet E1432E20 (Ver. 2.0)
11
ELPIDA [ ELPIDA MEMORY ]
