欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDD1208ALTA-7A 参数 Datasheet PDF下载

EDD1208ALTA-7A图片预览
型号: EDD1208ALTA-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 128 M位同步DRAM是双倍数据速率( 4 -银行, SSTL_2 ) [128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2)]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 78 页 / 1650 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDD1208ALTA-7A的Datasheet PDF文件第24页浏览型号EDD1208ALTA-7A的Datasheet PDF文件第25页浏览型号EDD1208ALTA-7A的Datasheet PDF文件第26页浏览型号EDD1208ALTA-7A的Datasheet PDF文件第27页浏览型号EDD1208ALTA-7A的Datasheet PDF文件第29页浏览型号EDD1208ALTA-7A的Datasheet PDF文件第30页浏览型号EDD1208ALTA-7A的Datasheet PDF文件第31页浏览型号EDD1208ALTA-7A的Datasheet PDF文件第32页  
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA  
10. Auto Precharge  
During a read or write command cycle, A10 controls auto precharge. A10 high in the read or write command (read  
with auto precharge command or write with auto precharge command), auto precharge is selected and begin  
automatically.  
The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the  
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.  
In read cycle, once auto precharge starts, an activate command to the bank can be issued after tRP is satisfied.  
In write cycle, tDAL must be satisfied to issue the next activate command to the bank being precharged.  
10.1 Read with Auto Precharge  
When a read with auto precharge command is issued, the auto precharge begins (Burst length / 2) clocks later from  
a read with auto precharge command.  
Burst length = 4  
T0  
T1  
T2  
T3  
T4  
T5  
Burst length / 2 cycle  
tRP  
CLK  
/CLK  
CKE  
/CAS latency = 2  
Command  
READA  
ACT  
Auto precharge starts  
Hi-Z  
DQ  
Q1  
Q2  
Q3  
Q4  
/CAS latency = 2.5  
READA  
ACT  
Command  
Auto precharge starts  
Hi-Z  
DQ  
Q1  
Q2  
Q3  
Q4  
(When tRAS is satisfied)  
Remark READA means Read with Auto Precharge command  
28  
Preliminary Data Sheet E0136E30  
 复制成功!