EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
9. Precharge
9.1 Read to Precharge Command Interval
The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is
issued, precharge operation performed and the DDR SDRAM enters the idle state after tRP is satisfied. The
parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
/CAS latency = 2
: (burst length/2) clocks after the read command is issued.
/CAS latency = 2.5 : (burst length/2) clocks after the read command is issued.
Burst length = 4
T5
T0
T1
T2
T3
T4
CLK
/CLK
CKE
/CAS latency = 2
Command
READ
PRE
Hi-Z
Hi-Z
DQS
DQ
Q1
Q2
Q3
Q4
/CAS latency = 2.5
READ
PRE
Command
Hi-Z
Hi-Z
DQS
DQ
Q1
Q2
Q3
Q4
(Must satisfy tRAS)
26
Preliminary Data Sheet E0136E30
ELPIDA [ ELPIDA MEMORY ]
