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EBE11ED8ABFA-4A-E 参数 Datasheet PDF下载

EBE11ED8ABFA-4A-E图片预览
型号: EBE11ED8ABFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR2 SDRAM DIMM ( 128M字× 72位, 2级) [1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 22 页 / 174 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE11ED8ABFA  
Parameter  
Symbol Grade  
IDD6  
max.  
108  
Unit  
mA  
Test condition  
Self Refresh Mode;  
CK and /CK at 0V;  
CKE 0.2V;  
Self-refresh current  
Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING  
all bank interleaving reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);  
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),  
tRCD = 1 × tCK (IDD);  
CKE is H, CS is H between valid commands;  
Address bus inputs are STABLE during DESELECTs;  
Data pattern is same as IDD4W;  
Operating current  
-5C  
IDD7  
2970  
2772  
mA  
mA  
(Bank interleaving)  
(Another rank is in IDD2P)  
-4A  
Operating current  
-5C  
IDD7  
3465  
3240  
(Bank interleaving)  
(Another rank is in IDD3N)  
-4A  
Notes: 1. IDD specifications are tested after the device is properly initialized.  
2. Input slew rate is specified by AC Input Test Condition.  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD  
values must be met with all combinations of EMRS bits 10 and 11.  
5. Definitions for IDD  
L is defined as VIN VIL (AC) (max.)  
H is defined as VIN VIH (AC) (min.)  
STABLE is defined as inputs stable at an H or L level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between H and L every other clock cycle (once per two clocks) for address and control  
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals  
not including masks or strobes.  
6. Refer to AC Timing for IDD Test Conditions.  
AC Timing for IDD Test Conditions  
For purposes of IDD testing, the following parameters are to be utilized.  
DDR2-533  
DDR2-400  
Parameter  
CL(IDD)  
4-4-4  
4
3-3-3  
3
Unit  
tCK  
ns  
tRCD(IDD)  
tRC(IDD)  
15  
15  
55  
55  
ns  
tRRD(IDD)  
tCK(IDD)  
7.5  
3.75  
40  
7.5  
5
ns  
ns  
tRAS(min.)(IDD)  
tRAS(max.)(IDD)  
tRP(IDD)  
40  
ns  
70000  
15  
70000  
15  
ns  
ns  
tRFC(IDD)  
105  
105  
ns  
Data Sheet E0379E40 (Ver. 4.0)  
12  
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