EBE11ED8ABFA
-5C
533
-4A
400
min.
Frequency (Mbps)
Parameter
Symbol min.
max.
max.
Unit
ns
Notes
Active bank A to active bank B
command period
tRRD
7.5
7.5
Write recovery time
tWR
15
15
ns
Auto precharge write recovery +
precharge time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
tWTR
tRTP
tCK
ns
1
Internal write to read command delay
7.5
10
Internal read to precharge command
delay
7.5
7.5
ns
Exit self refresh to a non-read command tXSNR tRFC + 10
tRFC + 10
200
ns
Exit self refresh to a read command
tXSRD 200
tCK
Exit precharge power down to any non-
read command
tXP
2
2
2
2
tCK
tCK
Exit active power down to read
command
tXARD
3
Exit active power down to read
command
tXARDS 6 − AL
6 − AL
tCK
2, 3
(slow exit/low power mode)
CKE minimum pulse width (high and
low pulse width)
tCKE
tOIT
3
3
tCK
ns
Output impedance test driver delay
0
12
0
12
Auto refresh to active/auto refresh
command time
tRFC
tREFI
105
105
ns
Average periodic refresh interval
7.8
7.8
µs
Minimum time clocks remains ON after
CKE asynchronously drops low
tDELAY tIS + tCK + tIH
tIS + tCK + tIH
ns
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
CK
DQS
/CK
/DQS
tIS
tIH
tIS
tIH
tDS tDH
tDS tDH
VDDQ
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E0379E40 (Ver. 4.0)
16
ELPIDA [ ELPIDA MEMORY ]
