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EBE11ED8ABFA-4A-E 参数 Datasheet PDF下载

EBE11ED8ABFA-4A-E图片预览
型号: EBE11ED8ABFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR2 SDRAM DIMM ( 128M字× 72位, 2级) [1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 22 页 / 174 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE11ED8ABFA  
ODT DC Electrical Characteristics (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V)  
(DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
Rtt1(eff)  
Rtt2(eff)  
VM  
min.  
60  
typ.  
75  
max.  
90  
Unit  
Note  
Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω  
Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω  
Deviation of VM with respect to VDDQ/2  
1
1
1
120  
3.75  
150  
180  
+3.75  
%
Note: 1. Test condition for Rtt measurements.  
Measurement Definition for Rtt(eff)  
Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.  
VIH(AC), and VDDQ values defined in SSTL_18.  
VIH(AC) VIL(AC)  
Rtt(eff) =  
I(VIH(AC)) I(VIL(AC))  
Measurement Definition for VM  
Measure voltage (VM) at test pin (midpoint) with no load.  
2 × VM  
VDDQ  
× 100%  
VM =  
1  
OCD Default Characteristics (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V)  
(DDR2 SDRAM Component Specification)  
Parameter  
min.  
12.6  
0
typ.  
18  
max.  
23.4  
4
Unit  
Notes  
1
Output impedance  
Pull-up and pull-down mismatch  
Output slew rate  
1, 2  
3, 4  
1.5  
4.5  
V/ns  
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;  
(VOUTVDDQ)/IOH must be less than 23.4for values of VOUT between VDDQ and VDDQ280mV.  
Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;  
VOUT/IOL must be less than 23.4for values of VOUT between 0V and 280mV.  
2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and  
voltage.  
3. Slew rate measured from VIL(AC) to VIH(AC).  
4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate  
as measured from AC to AC. This is guaranteed by design and characterization.  
Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)  
(DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
CI1  
Pins  
max.  
min.  
2
Unit  
pF  
Note  
Address, /RAS, /CAS,  
/WE, /CS, CKE, ODT  
Input capacitance  
1
1
3
Input capacitance  
CI2  
CK, /CK  
2
pF  
Data and DQS input/output  
capacitance  
CO  
DQ, DQS, /DQS, DM, CB  
4
pF  
Data Sheet E0379E40 (Ver. 4.0)  
14  
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