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EBE11ED8ABFA-4A-E 参数 Datasheet PDF下载

EBE11ED8ABFA-4A-E图片预览
型号: EBE11ED8ABFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR2 SDRAM DIMM ( 128M字× 72位, 2级) [1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 22 页 / 174 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE11ED8ABFA  
DC Characteristics 1 (TC = 0 to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)  
Parameter  
Symbol Grade  
max.  
Unit  
mA  
Test condition  
Operating current  
(ACT-PRE)  
(Another rank is in IDD2P)  
-5C  
IDD0  
1080  
927  
one bank; tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-4A  
Operating current  
(ACT-PRE)  
(Another rank is in IDD3N)  
-5C  
IDD0  
1575  
1395  
mA  
mA  
-4A  
one bank; IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
Operating current  
(ACT-READ-PRE)  
(Another rank is in IDD2P)  
-5C  
IDD1  
1215  
1062  
-4A  
tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data pattern is same as IDD4W  
Operating current  
(ACT-READ-PRE)  
(Another rank is in IDD3N)  
-5C  
IDD1  
1710  
1530  
mA  
mA  
-4A  
all banks idle;  
tCK = tCK (IDD);  
CKE is L;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
-5C  
IDD2P  
180  
144  
450  
360  
540  
450  
Precharge power-down  
standby current  
-4A  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
-5C  
IDD2Q  
Precharge quiet standby  
current  
mA  
mA  
-4A  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-5C  
IDD2N  
Idle standby current  
-4A  
all banks open;  
Fast PDN Exit  
tCK = tCK (IDD);  
MRS(12) = 0  
CKE is L;  
-5C  
IDD3P-F  
-4A  
720  
630  
450  
360  
mA  
mA  
Active power-down  
standby current  
Other control and address bus  
inputs are STABLE;  
-5C  
IDD3P-S  
-4A  
Slow PDN Exit  
MRS(12) = 1  
Data bus inputs are FLOATING  
all banks open;  
-5C  
IDD3N  
1170  
1080  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Active standby current  
mA  
-4A  
Operating current  
all banks open, continuous burst reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
-5C  
IDD4R  
1800  
1422  
mA  
mA  
mA  
(Burst read operating)  
(Another rank is in IDD2P)  
-4A  
Operating current  
(Burst read operating)  
(Another rank is in IDD3N)  
-5C  
IDD4R  
2295  
1890  
-4A  
Data pattern is same as IDD4W  
Operating current  
(Burst write operating)  
(Another rank is in IDD2P)  
all banks open, continuous burst writes;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-5C  
IDD4W  
1800  
1422  
-4A  
Operating current  
-5C  
IDD4W  
2295  
1890  
mA  
mA  
mA  
(Burst write operating)  
(Another rank is in IDD3N)  
-4A  
Auto-refresh current  
(Another rank is in IDD2P)  
-5C  
IDD5  
2340  
2142  
tCK = tCK (IDD);  
-4A  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Auto-refresh current  
(Another rank is in IDD3N)  
-5C  
IDD5  
2835  
2610  
-4A  
Data Sheet E0379E40 (Ver. 4.0)  
11  
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