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EBE11ED8ABFA-4A-E 参数 Datasheet PDF下载

EBE11ED8ABFA-4A-E图片预览
型号: EBE11ED8ABFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR2 SDRAM DIMM ( 128M字× 72位, 2级) [1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 22 页 / 174 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE11ED8ABFA  
AC Characteristics (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)  
(DDR2 SDRAM Component Specification)  
-5C  
533  
-4A  
400  
Frequency (Mbps)  
Parameter  
Symbol min.  
max.  
5
min.  
3
max.  
5
Unit  
tCK  
ns  
Notes  
/CAS latency  
CL  
4
Active to read or write command delay tRCD  
15  
15  
15  
15  
Precharge command period  
tRP  
tRC  
tAC  
ns  
Active to active/auto refresh command  
time  
55  
55  
ns  
DQ output access time from CK, /CK  
500  
+500  
+450  
0.55  
0.55  
600  
500  
0.45  
0.45  
+600  
+500  
0.55  
0.55  
ps  
DQS output access time from CK, /CK tDQSCK 450  
ps  
CK high-level width  
CK low-level width  
tCH  
tCL  
0.45  
0.45  
tCK  
tCK  
min.  
(tCL, tCH)  
min.  
(tCL, tCH)  
CK half period  
tHP  
ps  
Clock cycle time  
tCK  
tDH  
tDS  
3750  
225  
8000  
5000  
275  
8000  
ps  
ps  
ps  
DQ and DM input hold time  
DQ and DM input setup time  
5
4
100  
150  
Control and Address input pulse width  
for each input  
tIPW  
tDIPW  
tHZ  
0.6  
0.6  
tCK  
tCK  
ps  
DQ and DM input pulse width for each  
input  
0.35  
0.35  
Data-out high-impedance time from  
CK,/CK  
tAC max.  
tAC max.  
tAC max.  
tAC max.  
Data-out low-impedance time from  
CK,/CK  
tLZ  
tAC min.  
tAC min.  
ps  
DQS-DQ skew for DQS and associated  
DQ signals  
tDQSQ  
300  
400  
350  
450  
ps  
DQ hold skew factor  
tQHS  
tQH  
ps  
ps  
DQ/DQS output hold time from DQS  
tHP – tQHS  
tHP – tQHS  
Write command to first DQS latching  
transition  
tDQSS WL 0.25  
WL + 0.25  
WL 0.25  
WL + 0.25  
tCK  
DQS input high pulse width  
tDQSH 0.35  
tDQSL 0.35  
0.35  
0.35  
0.2  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ps  
DQS input low pulse width  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
tDSS  
tDSH  
0.2  
0.2  
2
0.2  
Mode register set command cycle time tMRD  
2
Write preamble setup time  
Write postamble  
tWPRES 0  
0
tWPST 0.4  
tWPRE 0.25  
0.6  
0.4  
0.6  
Write preamble  
0.25  
475  
350  
0.9  
Address and control input hold time  
Address and control input setup time  
Read preamble  
tIH  
tIS  
375  
250  
5
4
ps  
tRPRE 0.9  
tRPST 0.4  
1.1  
1.1  
tCK  
tCK  
ns  
Read postamble  
0.6  
0.4  
0.6  
Active to precharge command  
Active to auto-precharge delay  
tRAS  
tRAP  
40  
70000  
40  
70000  
tRCD min.  
tRCD min.  
ns  
Data Sheet E0379E40 (Ver. 4.0)  
15  
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