EBE10AD4AGFA
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal)
SDRAM
PLL
120Ω
OUT1
120Ω
SDRAM
CK0
IN
Register 1
/CK0
120Ω
OUT'N'
C
120Ω
Feedback in
C
Feedback out
Register 2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl
be set to 0ns (nominal).
2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the
input pin of the PLL as possible.
Preliminary Data Sheet E0865E11 (Ver. 1.1)
9
ELPIDA [ ELPIDA MEMORY ]
