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EBE10AD4AGFA 参数 Datasheet PDF下载

EBE10AD4AGFA图片预览
型号: EBE10AD4AGFA
PDF下载: 下载PDF文件 查看货源
内容描述: 注册1GB DDR2 SDRAM DIMM [1GB Registered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 23 页 / 199 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE10AD4AGFA的Datasheet PDF文件第1页浏览型号EBE10AD4AGFA的Datasheet PDF文件第2页浏览型号EBE10AD4AGFA的Datasheet PDF文件第3页浏览型号EBE10AD4AGFA的Datasheet PDF文件第4页浏览型号EBE10AD4AGFA的Datasheet PDF文件第6页浏览型号EBE10AD4AGFA的Datasheet PDF文件第7页浏览型号EBE10AD4AGFA的Datasheet PDF文件第8页浏览型号EBE10AD4AGFA的Datasheet PDF文件第9页  
EBE10AD4AGFA  
Serial PD Matrix  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
Number of bytes utilized by module  
manufacturer  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
128 bytes  
256 bytes  
Total number of bytes in serial PD  
device  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
0
0
1
08H  
0EH  
0BH  
60H  
48H  
00H  
05H  
DDR2 SDRAM  
Number of row address  
Number of column address  
Number of DIMM ranks  
Module data width  
14  
11  
1
72  
Module data width continuation  
0
Voltage interface level of this assembly 0  
SSTL 1.8V  
DDR SDRAM cycle time, CL = 5  
-6E  
9
0
0
1
1
0
0
0
0
30H  
3.0ns*1  
-5C  
-4A  
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
3DH  
50H  
3.75ns*1  
5.0ns*1  
SDRAM access from clock (tAC)  
-6E  
10  
11  
0
1
0
0
0
1
0
1
45H  
0.45ns*1  
-5C  
-4A  
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
50H  
60H  
0.5ns*1  
0.6ns*1  
ECC, Address/  
Command Parity  
DIMM configuration type  
0
0
0
0
0
1
1
0
06H  
12  
13  
14  
15  
Refresh rate/type  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
82H  
04H  
04H  
00H  
7.8µs  
× 4  
× 4  
0
Primary SDRAM width  
Error checking SDRAM width  
Reserved  
SDRAM device attributes:  
Burst length supported  
16  
17  
18  
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0CH  
04H  
38H  
4,8  
SDRAM device attributes: Number of  
banks on SDRAM device  
4
SDRAM device attributes:  
/CAS latency  
3, 4, 5  
19  
20  
21  
DIMM Mechanical Characteristics  
DIMM type information  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
01H  
01H  
00H  
4.00mm max.  
Registered  
Normal  
SDRAM module attributes  
Weak Driver 50Ω  
ODT Support  
22  
23  
SDRAM device attributes: General  
0
0
0
0
0
0
1
1
03H  
Minimum clock cycle time at CL = 4  
-6E, -5C  
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
3DH  
50H  
3.75ns*1  
5.0ns*1  
-4A  
Maximum data access time (tAC) from  
clock at CL = 4  
24  
0
1
0
1
0
0
0
0
50H  
0.5ns*1  
-6E, -5C  
-4A  
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H  
50H  
0.6ns*1  
5.0ns*1  
25  
26  
27  
Minimum clock cycle time at CL = 3  
Maximum data access time (tAC) from  
clock at CL = 3  
0
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
60H  
3CH  
0.6ns*1  
15ns  
Minimum row precharge time (tRP)  
Preliminary Data Sheet E0865E11 (Ver. 1.1)  
5
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