欢迎访问ic37.com |
会员登录 免费注册
发布采购

EBE10AD4AGFA 参数 Datasheet PDF下载

EBE10AD4AGFA图片预览
型号: EBE10AD4AGFA
PDF下载: 下载PDF文件 查看货源
内容描述: 注册1GB DDR2 SDRAM DIMM [1GB Registered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 23 页 / 199 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE10AD4AGFA的Datasheet PDF文件第8页浏览型号EBE10AD4AGFA的Datasheet PDF文件第9页浏览型号EBE10AD4AGFA的Datasheet PDF文件第10页浏览型号EBE10AD4AGFA的Datasheet PDF文件第11页浏览型号EBE10AD4AGFA的Datasheet PDF文件第13页浏览型号EBE10AD4AGFA的Datasheet PDF文件第14页浏览型号EBE10AD4AGFA的Datasheet PDF文件第15页浏览型号EBE10AD4AGFA的Datasheet PDF文件第16页  
EBE10AD4AGFA  
Parameter  
Symbol Grade  
-6E  
max.  
Unit  
mA  
Test condition  
tCK = tCK (IDD);  
5440  
5030  
4630  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Auto-refresh current  
IDD5  
-5C  
-4A  
Self Refresh Mode;  
CK and /CK at 0V;  
Self-refresh current  
IDD6  
150  
mA  
mA  
CKE 0.2V;  
Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING  
all bank interleaving reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);  
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),  
tRCD = 1 × tCK (IDD);  
CKE is H, CS is H between valid commands;  
Address bus inputs are STABLE during DESELECTs;  
Data pattern is same as IDD4W;  
-6E  
-5C  
-4A  
6380  
6250  
5770  
Operating current  
(Bank interleaving)  
IDD7  
Notes: 1. IDD specifications are tested after the device is properly initialized.  
2. Input slew rate is specified by AC Input Test Condition.  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD  
values must be met with all combinations of EMRS bits 10 and 11.  
5. Definitions for IDD  
L is defined as VIN VIL (AC) (max.)  
H is defined as VIN VIH (AC) (min.)  
STABLE is defined as inputs stable at an H or L level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between H and L every other clock cycle (once per two clocks) for address and control  
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals  
not including masks or strobes.  
6. Refer to AC Timing for IDD Test Conditions.  
AC Timing for IDD Test Conditions  
For purposes of IDD testing, the following parameters are to be utilized.  
DDR2-667  
DDR2-533  
DDR2-400  
Parameter  
CL(IDD)  
5-5-5  
5
4-4-4  
4
3-3-3  
3
Unit  
tCK  
ns  
tRCD(IDD)  
tRC(IDD)  
15  
15  
15  
60  
60  
55  
ns  
tRRD(IDD)  
tCK(IDD)  
7.5  
3
7.5  
3.75  
45  
7.5  
5
ns  
ns  
tRAS(min.)(IDD)  
tRAS(max.)(IDD)  
tRP(IDD)  
45  
40  
ns  
70000  
15  
70000  
15  
70000  
15  
ns  
ns  
tRFC(IDD)  
105  
105  
105  
ns  
Preliminary Data Sheet E0865E11 (Ver. 1.1)  
12