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EBE10AD4AGFA 参数 Datasheet PDF下载

EBE10AD4AGFA图片预览
型号: EBE10AD4AGFA
PDF下载: 下载PDF文件 查看货源
内容描述: 注册1GB DDR2 SDRAM DIMM [1GB Registered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 23 页 / 199 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE10AD4AGFA的Datasheet PDF文件第2页浏览型号EBE10AD4AGFA的Datasheet PDF文件第3页浏览型号EBE10AD4AGFA的Datasheet PDF文件第4页浏览型号EBE10AD4AGFA的Datasheet PDF文件第5页浏览型号EBE10AD4AGFA的Datasheet PDF文件第7页浏览型号EBE10AD4AGFA的Datasheet PDF文件第8页浏览型号EBE10AD4AGFA的Datasheet PDF文件第9页浏览型号EBE10AD4AGFA的Datasheet PDF文件第10页  
EBE10AD4AGFA  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
7.5ns  
Minimum row active to row active delay  
28  
29  
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1EH  
3CH  
(tRRD)  
Minimum /RAS to /CAS delay (tRCD)  
15ns  
Minimum active to precharge time  
30  
(tRAS)  
0
0
1
0
1
1
0
1
2DH  
45ns  
-6E, -5C  
-4A  
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
28H  
01H  
40ns  
1GB  
31  
32  
Module rank density  
Address and command setup time  
before clock (tIS)  
-6E  
0
0
1
0
0
0
0
0
20H  
0.20ns*1  
-5C  
-4A  
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
25H  
35H  
0.25ns*1  
0.35ns*1  
Address and command hold time after  
clock (tIH)  
-6E  
33  
0
0
1
0
1
0
0
0
28H  
0.28ns*1  
-5C  
-4A  
0
0
0
1
1
0
1
0
1
1
0
0
0
0
0
0
38H  
48H  
0.38ns*1  
0.48ns*1  
Data input setup time before clock  
(tDS)  
34  
35  
0
0
0
1
0
0
0
0
10H  
0.10ns*1  
-6E, -5C  
-4A  
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
0
15H  
18H  
0.15ns*1  
0.18ns*1  
Data input hold time after clock (tDH)  
-6E  
-5C  
0
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
0
23H  
28H  
3CH  
0.23ns*1  
0.28ns*1  
15ns*1  
-4A  
36  
37  
Write recovery time (tWR)  
Internal write to read command delay  
(tWTR)  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
-6E, -5C  
-4A  
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H  
1EH  
10ns*1  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
39  
40  
Memory analysis probe characteristics 0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00H  
00H  
TBD  
Extension of Byte 41 and 42  
0
0
0
0
1
0
Undefined  
Active command period (tRC)  
-6E, -5C  
41  
0
0
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
0
0
3CH  
37H  
69H  
80H  
18H  
60ns*1  
55ns*1  
105ns*1  
8ns*1  
-4A  
Auto refresh to active/  
42  
43  
44  
Auto refresh command cycle (tRFC)  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
-6E  
0.24ns*1  
-5C  
-4A  
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
1EH  
23H  
0.30ns*1  
0.35ns*1  
Data hold skew (tQHS)  
-6E  
45  
0
0
1
0
0
0
1
0
22H  
0.34ns*1  
-5C  
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
0
1
1
0
28H  
2DH  
0FH  
00H  
0.40ns*1  
0.45ns*1  
15µs  
-4A  
46  
PLL relock time  
47 to 61  
Preliminary Data Sheet E0865E11 (Ver. 1.1)  
6