EBE10AD4AGFA
Pin Description
Pin name
Function
Address input
Row address
Column address
A0 to A13
A0 to A13
A0 to A9, A11
A10 (AP)
Auto precharge
BA0, BA1
Bank select address
Data input/output
DQ0 to DQ63
CB0 to CB7
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
/RAS
/CAS
/WE
/CS0
Chip select
CKE0
Clock enable
CK0
Clock input
/CK0
Differential clock input
DQS0 to DQS17, /DQS0 to /DQS17
Input and output data strobe
Clock input for serial PD
Data input/output for serial PD
Serial address input
SCL
SDA
SA0 to SA2
VDD
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
VDDSPD
VREF
VSS
ODT0
ODT control
/RESET
Par_In*2
/Err_Out*2
NC
Reset pin (forces register and PLL inputs low) *1
Parity bit for the address and control bus
Parity error found on the address and control bus
No connection
Note: 1. Reset pin is connected to both OE of PLL and reset to register.
2. /Err_Out (Pin No. 55) and Par_In (Pin No. 68) are for optional function to check address and command
parity.
Preliminary Data Sheet E0865E11 (Ver. 1.1)
4
ELPIDA [ ELPIDA MEMORY ]
