PRELIMINARY DATA SHEET
1GB Registered DDR2 SDRAM DIMM
EBE10AD4AGFA (128M words × 72 bits, 1 Rank)
Specifications
Features
• Density: 1GB
• Double-data-rate architecture; two data transfers per
clock cycle
• Organization
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
128M words × 72 bits, 1 rank
• Mounting 18 pieces of 512M bits DDR2 SDRAM
sealed in FBGA
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• Package: 240-pin socket type dual in line memory
module (DIMM)
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
PCB height: 30.0mm
Lead pitch: 1.0mm
• Differential clock inputs (CK and /CK)
Lead-free (RoHS compliant)
• DLL aligns DQ and DQS transitions with CK
transitions
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps/533Mbps/400Mbps (max.)
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Four internal banks for concurrent operation
(components)
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Interface: SSTL_18
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• /DQS can be disabled for single-ended Data Strobe
operation
• Precharge: auto precharge option for each burst
access
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Document No. E0865E11 (Ver. 1.1)
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006
ELPIDA [ ELPIDA MEMORY ]
