EBD21RD4ABNA
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
Timing Parameter Measured in Clock Cycle for Registered DIMM
Number of clock cycle
Parameter
Symbol
tWPD
tRPD
min.
max.
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
Write to read command delay (to input all data)
3 + BL/2
BL/2
tWRD
2 + BL/2
Burst stop command to write command delay
(CL = 3)
tBSTW
tBSTW
tBSTZ
tBSTZ
tRWD
tRWD
tHZP
2
(CL = 3.5)
3
Burst stop command to DQ High-Z
(CL = 3)
3
3
(CL = 3.5)
3.5
3.5
Read command to write command delay (to output all data)
(CL = 3)
2 + BL/2
3 + BL/2
3
(CL = 3.5)
Pre-charge command to High-Z
(CL = 3)
3
(CL = 3.5)
tHZP
3.5
2
3.5
2
Write command to data in latency
Write recovery
tWCD
tWR
1
Register set command to active or register set command
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
tMRD
tSNR
tSRD
tPDEN
tPDEX
2
10
200
1
1
Power down exit to command input
1
Preliminary Data Sheet E0273E20 (Ver. 2.0)
14
ELPIDA [ ELPIDA MEMORY ]
