EBD21RD4ABNA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V 0.2V)
Parameter
Symbol
CI1
Pins
max.
TBD
TBD
TBD
Unit
pF
Notes
1, 3
Address, /RAS, /CAS, /WE,
/CS, CKE
Input capacitance
Input capacitance
CI2
CK, /CK
pF
1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, CB, DM
pF
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
(DDR SDRAM device Specification)
-7A
-7B
-10
Parameter
Symbol
tCK
min.
max min.
max
12
min.
max
12
Unit
ns
Notes
10
Clock cycle time
(CL = 2)
7.5
12
12
10
10
(CL = 2.5)
tCK
tCH
tCL
7.5
7.5
12
10
12
ns
CK high-level width
CK low-level width
0.45
0.45
0.55 0.45
0.55 0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
min
(tCH, tCL)
min
—
min
(tCH, tCL)
CK half period
tHP
tAC
—
—
tCK
ns
(tCH, tCL)
DQ output access time from
CK, /CK
–0.75
0.75 –0.75
0.75 –0.75
0.75
–0.8
0.8
2, 11
DQS output access time from CK,
/CK
tDQSCK –0.75
0.75
0.5
–0.8
—
0.8
0.6
ns
ns
ns
ns
ns
2, 11
3
DQS to DQ skew
tDQSQ
tQH
—
0.5
—
—
DQ/DQS output hold time from
DQS
tHP – tQHS
—
tHP – tQHS
—
—
tHP – tQHS —
Data hold skew factor
tQHS
tHZ
0.75
0.75
0.75
—
1.0
Data-out high-impedance time
from CK, /CK
–0.75
0.75 –0.75
0.75 –0.75
–0.8
0.8
0.8
5, 11
6, 11
Data-out low-impedance time from
CK, /CK
tLZ
–0.75
0.75
–0.8
ns
Read preamble
tRPRE
tRPST
tDS
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.6
0.6
2
1.1
0.6
—
tCK
tCK
ns
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
8
8
7
tDH
—
—
—
ns
tDIPW
tWPRES
tWPRE
tWPST
—
—
—
ns
—
—
0
—
ns
0.25
0.4
—
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
0.6
9
Write command to first DQS
latching transition
tDQSS
0.75
0.2
1.25 0.75
1.25
—
0.75
0.2
1.25
—
tCK
tCK
tCK
DQS falling edge to CK setup time tDSS
—
—
0.2
0.2
DQS falling edge hold time from
CK
tDSH
0.2
—
0.2
—
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
—
—
0.35
0.35
—
—
0.35
0.35
—
—
tCK
tCK
Preliminary Data Sheet E0273E20 (Ver. 2.0)
12
ELPIDA [ ELPIDA MEMORY ]
