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EBD21RD4ABNA-7A 参数 Datasheet PDF下载

EBD21RD4ABNA-7A图片预览
型号: EBD21RD4ABNA-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 注册2GB DDR SDRAM DIMM [2GB Registered DDR SDRAM DIMM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 19 页 / 176 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBD21RD4ABNA  
Electrical Specifications  
All voltages are referenced to VSS (GND).  
After power up, wait more than 200 µs and then, execute power on sequence and auto refresh before proper  
device operation is achieved.  
Absolute Maximum Ratings  
Parameter  
Symbol  
VT  
Value  
Unit  
V
Note  
Voltage on any pin relative to VSS  
Supply voltage relative to VSS  
Short circuit output current  
Power dissipation  
–1.0 to +3.6  
–1.0 to +3.6  
50  
VDD, VDDQ  
IOUT  
PT  
V
mA  
W
18  
Operating ambient temperature  
Storage temperature  
TA  
0 to +70  
–55 to +125  
°C  
°C  
1
Tstg  
Note: 1. DDR SDRAM device specification  
Caution  
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause  
permanent damage. The device is not meant to be operated under conditions outside the limits  
described in the operational section of this specification. Exposure to Absolute Maximum Rating  
conditions for extended periods may affect device reliability.  
DC Operating Conditions (TA = 0 to +70°C)  
Parameter  
Symbol  
VDD,VDDQ  
VSS  
Min  
Typ  
2.5  
0
Max  
2.7  
0
Unit  
V
Notes  
1
Supply voltage  
2.3  
0
V
Input reference voltage  
Termination voltage  
Input high voltage  
Input low voltage  
VREF  
0.49 × VDDQ  
VREF – 0.04  
VREF + 0.15  
–0.3  
0.50 × VDDQ 0.51 × VDDQ  
V
VTT  
VREF  
VREF + 0.04  
VDDQ + 0.3  
VREF – 0.15  
V
VIH (DC)  
VIL (DC)  
V
2
3
V
Input voltage level,  
CK and /CK inputs  
VIN (DC)  
VIX (DC)  
VID (DC)  
–0.3  
VDDQ + 0.3  
V
V
V
4
Input differential cross point  
voltage, CK and /CK inputs  
0.5 × VDDQ 0.2V 0.5 × VDDQ  
0.36  
0.5 × VDDQ + 0.2V  
VDDQ + 0.6  
Input differential voltage,  
CK and /CK inputs  
5, 6  
Notes: 1.VDDQ must be lower than or equal to VDD.  
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.  
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.  
4. VIN (DC) specifies the allowable dc execution of each differential input.  
5. VID (dc) specifies the input differential voltage required for switching.  
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V  
if measurement.  
Preliminary Data Sheet E0273E20 (Ver. 2.0)  
10  
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