EBD21RD4ABNA
-7A
-7B
-10
Parameter
Symbol
tIS
min.
max
—
min.
max
—
min.
max
—
Unit
ns
Notes
8
Address and control input setup
time
0.9
0.9
2.2
2
0.9
0.9
2.2
2
1.1
1.1
2.5
2
Address and control input hold
time
tIH
—
—
—
—
—
—
—
—
—
ns
8
7
Address and control input pulse
width
tIPW
tMRD
tRAS
tRC
ns
Mode register set command cycle
time
tCK
Active to Precharge command
period
45
120000 45
120000 50
120000 ns
Active to Active/Auto refresh
command period
67.5
—
67.5
—
70
—
ns
Auto refresh to Active/Auto refresh
command period
tRFC
tRCD
tRP
75
20
20
—
—
—
75
20
20
—
—
—
80
20
20
—
—
—
ns
ns
ns
Active to Read/Write delay
Precharge to active command
period
Active to auto precharge delay
tRAP
tRCD min. —
tRCD min. —
tRCD min. —
ns
ns
ns
Active to active command period tRRD
15
15
—
—
15
15
—
—
15
15
—
—
Write recovery time
tWR
Auto precharge write recovery
and precharge time
(tWR/tCK)
+(tRP/tCK)
(tWR/tCK)
+(tRP/tCK)
(tWR/tCK)
+(tRP/tCK)
tDAL
—
—
—
tCK
13
Internal write to Read command
delay
tWTR
tREF
1
—
1
—
1
—
tCK
µs
Average periodic refresh interval
—
7.8
—
7.8
—
7.8
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
Preliminary Data Sheet E0273E20 (Ver. 2.0)
13
ELPIDA [ ELPIDA MEMORY ]
