EBD21RD4ABNA
Byte No. Function described
Minimum active to precharge time
(tRAS)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
45ns
30
0
0
1
0
1
1
0
1
2DH
-7A, -7B
-10
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
32H
01H
50ns
2 banks
1GB
31
32
Module bank density
Address and command setup time
before clock (tIS)
-7A, -7B
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
90H
B0H
90H
B0H
50H
0.9ns*3
1.1ns*3
0.9ns*3
1.1ns*3
0.5ns*3
-10
Address and command hold time after
clock (tIH)
-7A, -7B
33
-10
Data input setup time before clock
(tDS)
-7A, -7B
34
35
-10
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H
50H
0.6ns*3
0.5ns*3
Data input hold time after clock (tDH)
-7A, -7B
-10
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
60H
00H
0.6ns*3
36 to 40
41
Superset information
Future use
Active command period (tRC)
-7A, -7B
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
43H
46H
67.5ns*3
70ns*3
-10
Auto refresh to active/
Auto refresh command cycle (tRFC)
-7A, -7B
42
0
1
0
0
1
0
1
1
4BH
75ns*3
-10
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
50H
30H
80ns*3
12ns*3
43
44
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-7A, -7B
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
1
1
0
0
0
0
1
32H
3CH
75H
500ps*3
600ps*3
750ps*3
-10
Data hold skew (tQHS)
-7A, -7B
45
-10
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0H
00H
00H
1000ps*3
Future use
Initial
46 to 61
62
Superset information
SPD revision
Checksum for bytes 0 to 62
-7A
63
1
0
0
0
1
1
0
1
8DH
141
-7B
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
1
0
0
B8H
9BH
7FH
7FH
FEH
00H
184
155
-10
64
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
65
66
Elpida Memory
67 to 71
*2 (ASCII-8bit
code)
72
Manufacturing location
×
×
×
×
×
×
×
×
××
73
74
75
76
Module part number
Module part number
Module part number
Module part number
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
1
0
0
0
45H
42H
44H
32H
E
B
D
2
Preliminary Data Sheet E0273E20 (Ver. 2.0)
6
ELPIDA [ ELPIDA MEMORY ]
