MR
LDCW
D[15:0]
tMR
tPWLD
tHDW
tSDW
Valid Data
Figure 7: Reset and Initialization Sequence
BIT 31
BIT 32
ARINC DATA
/DR1, /DR2
SEL
tDDRN
tHSEL
tSSEL
/OE1, /OE2
D[15:0]
tPWOE
tOEOE
tDDROE
tDOEDR
Word 1 Valid
Word 2 Valid
tDTS
tDDR
Figure 8: Receiver Read Operation and Timing
Figure 9: Transmitter Write Operation and Timing
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 11 of 14