B L O C K D I A G R A M
P I N S D E S C R I P T I O N
clk
PIN
TYPE
DESCRIPTION
Opcode
Decoder
reset
clk
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
Global clock
ALU
reset
Global synchronous reset
Data bus from Internal Data Memory
Data bus from user SFRs
Input data bus from Program Memory
Data bus from External Data Memory
External interrupt 0 line
External interrupt 1 line
External interrupt 2 line
External interrupt 3 line
External interrupt 4 line
External interrupt 5 line
External interrupt 6 line
DoCD™ data input
prgdatai(7:0)
prgdatao(7:0)
prgdataz
ramdatai[7:0]
sfrdatai[7:0]
prgdatai[7:0]
xramdatai[7:0]
int0
Program
Memory
Interface
prgaddr(23:0)
prgrd
Control Unit
prgwr
xramdatai(7:0)
xramdatao(7:0)
xramdataz
int0
int1
int2
int3
int4
int5
int6
External
Memory
Interface
int1
xramaddr(23:0)
xramrd
Interrupt
int2
Controller
xramwr
int3
int4
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
Internal Data
Memory
int5
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
Interface
int6
ramwe
docddatai
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
t0
I/O Ports
sfrdatai(7:0)
sfrdatao(7:0)
sfraddr(7:0)
sfroe
Port 0 input
User SFR
Interface
Port 1 input
Port 2 input
sfrwe
Port 3 input
docddatai
docddatao
docdclk
Timer 0 clock line
Power
Management
Unit
stop
DoCD™
Debug Unit
pmm
gate0
Timer 0 clock line gate control
Timer 1 clock line
t1
gate1
Timer 1 clock line gate control
Timer 2 clock line
Floating
Multiply
t2
Point Unit
Divide Unit
t2ex
Timer 2 control
capture0
capture1
capture2
capture3
rxd0i
Timer 2 capture 0 line
Timer 2 capture 1 line
Timer 2 capture 2 line
Timer 2 capture 3 line
Serial receiver input 0
Serial receiver input 1
Master I2C clock line input
Master I2C data input
Slave I2C clock line input
Slave I2C data input
SPI slave select
t0
t2
gate0
t1
Timer 2
Timers 0 & 1
t2ex
gate1
capture0
capture1
capture2
capture3
Compare
Watchdog
Timer
rxd1i
Capture Unit
mscli
msdai
rxd1o
sscli
rxd0o
rxd0i
txd0
UART 1
UART 0
SPI Unit
rxd1i
ssdai
txd1
ss
so
msclhs
mscli
si
SPI slave input
si
Master
mi
SPI master input
mo
msclo
msdai
msdao
I2C Unit
mi
scki
SPI clock input
scko
scki
sckz
ss
ramdatao[7:0]
ramaddr[7:0]
ramoe
ramwe
sfrdatao[7:0]
sfraddr[7:0]
sfroe
output Data bus for Internal Data Memory
output Internal Data Memory address bus
output Internal Data Memory output enable
output Internal Data Memory write enable
output Data bus for user SFRs
sscli
ssclo
ssdai
ssdao
Slave
I2C Unit
sso(7:0)
output User SFRs address bus
output User SFRs output enable
sfrwe
output User SFRs write enable
prgaddr[23:0]
output Program Memory address bus
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
