○ 2 priority levels
● User programmable External Data Memory
Wait States solution for wide range of
memories speed
○ Up to 7 external interrupt sources
○ Up to 8 interrupt sources from peripherals
● Four 8-bit I/O Ports
● De-multiplexed Address/Data bus to allow
easy connection to memory
○ Bit addressable data direction for each line
○ Read/write of single line and 8-bit group
● Three 16-bit timer/counters
○ Timers clocked by internal source
○ Auto reload 8/16-bit timers
● Interface for additional Special Function
Registers
● Fully synthesizable, static synchronous de-
sign with positive edge clocking and no in-
ternal tri-states
● Scan test ready
○ Externally gated event counters
● 1.3 GHz virtual clock frequency in a 0.35u
● Full-duplex serial port
technological process
○ Synchronous mode, fixed baud rate
○ 8-bit asynchronous mode, fixed baud rate
○ 9-bit asynchronous mode, fixed baud rate
○ 9-bit asynchronous mode, variable baud rate
● I2C bus controller - Master
○ 7-bit and 10-bit addressing modes
○ NORMAL, FAST, HIGH speeds
○ Multi-master systems supported
○ Clock arbitration and synchronization
○ User defined timings on I2C lines
○ Wide range of system clock frequencies
○ Interrupt generation
P E R I P H E R A L S
● DoCD™ debug unit
○ Processor execution control
○
○
○
○
Run
Halt
Step into instruction
Skip instruction
○ Read-write all processor contents
○
○
○
○
○
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
● I2C bus controller - Slave
○ Hardware execution breakpoints
○ NORMAL speed 100 kbs
○
○
○
○
Program Memory
○ FAST speed 400 kbs
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ HIGH speed 3400 kbs
○ Wide range of system clock frequencies
○ User defined data setup time on I2C lines
○ Interrupt generation
○ Hardware breakpoints activated at a certain
○
○
○
○
○
Program address (PC)
● SPI – Master and Slave Serial Peripheral
Address by any write into memory
Address by any read from memory
Address by write into memory a required data
Address by read from memory a required data
Interface
○ Supports speeds up ¼ of system clock
○
○
Mode fault error
Write collision error
○ Three wire communication interface
● Power Management Unit
○ Power management mode
○ Switchback feature
○ Four transfer formats supported
○ System errors detection
○ Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
○ Interrupt generation
○ Stop mode
● Programmable Watchdog Timer
● Extended Interrupt Controller
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
