36996
P E R F O R M A N C E
40000
35000
30000
25000
20000
15000
10000
5000
The following tables give a survey about the
Core area and performance in ASICs Devices
(all key features have been included):
Device
Optimization
area
Fmax
0.25u typical
100 MHz
0.25u typical
speed
200 MHz
Core performance in ASIC devices
1550
268
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and their improvements
are shown in table below. An improvement was
computed as {80C51 clock periods} divided by
{DR80390XP clock periods} required to exe-
cute an identical function. More details are
available in core documentation.
0
80C51 (12MHz)
DR80390XP (200MHz)
80C310 (33MHz)
Area utilized by the each unit of DR80390XP
core in vendor specific technologies is summa-
rized in table below.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
Improvement
7,20
Area
Component
[Gates]
5500
300
[FFs]
250
32
-
6,00
6,00
7,20
7,20
6,00
6,00
7,20
CPU*
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR0 & DPTR1 auto-switch
Timed Access protection
Interrupt Controller
INT2-INT6
100
100
-
50
8
100
10
40
25
5
500
10,67
9,60
350
8-bit division
Power Management Unit
I/O ports
50
16-bit addition
7,20
7,64
9,75
7,20
7,43
9,04
7,58
400
35
16-bit subtraction
Timers
600
600
700
700
900
550
450
550
400
1700
50
60
16-bit multiplication
Timer 2
32-bit addition
UART0
60
32-bit subtraction
UART1
60
32-bit multiplication
Master I2C Unit
Slave I2C Unit
SPI Unit
120
70
Average speed improvement:
55
Compare Capture Unit
Watchdog Timer
Multiply Divide Unit
60
45
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DR80390XP per-
formance in terms of Dhrystone/sec and VAX
MIPS rating.
105
Total area
14600
1090
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
Clock
frequency
12 MHz
Dhry/sec
(VAX MIPS)
268 (0.153)
1550 (0.882)
Device
Target
80C51
-
-
80C310
33 MHz
DR80390XP
0.25u
200 MHz 36996 (21.000)
Core performance in terms of Dhrystones
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