♦
♦
♦
Synthesis scripts
S Y M B O L
Example application
Technical support
clk
◊ IP Core implementation support
◊ 3 months maintenance
reset
ramdatai(7:0)
ramdatao(7:0)
●
Delivery the IP Core updates, minor and
major versions changes
ramaddr(7:0)
ramoe
ramwe
●
●
Delivery the documentation updates
Phone & email support
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrdatai(7:0)
prgdatai(7:0)
sfrwe
L I C E N S I N G
prgdatao(7:0)
prgdataz
prgaddr(23:0)
prgrd
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
prgwr
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
xramdatai(7:0) xramdatao(7:0)
xramdataz
xramaddr(23:0)
xramrd
int0
int1
int2
int3
int4
int5
int6
xramwr
docddatai
docddatao
docdclk
stop
pmm
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
t0
gate0
t1
○ Encrypted Netlist only
gate1
● Unlimited Designs license for
○ HDL Source
t2
t2ex
○ Netlist
capture0
capture1
capture2
capture3
● Upgrade from
○ HDL Source to Netlist
rxd0i
rxd0o
txd0
○ Single Design to Unlimited Designs
rxd1i
rxd1o
txd1
msclhs
msclo
mscli
msdai
msdao
sscli
ssclo
ssdai
ssdao
ss
si
sso(7:0)
so
mi
mo
scki
scko
sckz
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
