ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
PIN
port3o[7:0]
prgaddr[15:0]
prgdatao[7:0]
prgramwr
TYPE
DESCRIPTION
output Port 3 output
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
output Internal program memory address bus
output Data bus for internal program memory
output Internal program memory write
sxdmaddr[15:0] output Sync XDATA memory address bus
(SXDM)
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
sxdmdatao[7:0] output Data bus for Sync XDATA memory
(SXDM)
sxdmoe
sxdmwe
xaddr[23:0]
xdatao[7:0]
xdataz
xprgrd
xprgwr
xdatard
xdatawr
ramaddr[7:0]
ramdatao[7:0]
ramoe
ramwe
sfraddr[6:0]
sfrdatao[7:0]
sfroe
output Sync XDATA memory read (SXDM)
output Sync XDATA memory write (SXDM)
output Address bus for external memories
output Data bus for external memories
output Turn xdata bus into ‘Z’ state
output External program memory read
output External program memory write
output External data memory read
output External data memory write
output Internal Data Memory address bus
output Data bus for internal data memory
output Internal data memory output enable
output Internal data memory write enable
output Address bus for user SFR’s
output Data bus for user SFR’s
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains mem-
ory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It per-
forms the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
output User SFR’s read enable
sfrwe
output User SFR’s write enable
tdo
output DoCD™ TAP data output
output DoCD™ return clock line
output DoCD™ accessing data
rtck
Synchronous
eXternal
Data
Memory
(SXDM) Interface – contains XDATA memory
access related logic allowing fast access to
synchronous memory devices. It performs the
external Data Memory addressing and data
transfers. This memory can be used to store
large variables frequently accessed by CPU,
improving overall performance of application.
debugacs
coderun
pmm
output CPU is executing an instruction
output Power management mode indicator
output Stop mode indicator
stop
rxd0o
output Serial receiver output 0
rxd1o
output Serial receiver output 1
txd0
output Serial transmitter output 0
output Serial transmitter output 1
output Master/Slave I2C clock output
output High speed Master I2C clock line
output Master/Slave I2C data output
output SPI slave select lines
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
txd1
sclo
sclhs
sdao
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
sso[7:0]
so
output SPI slave output
mo
output SPI master output
scko
output SPI clock output
scken
output SPI clock line tri-state buffer control
output SPI slave output enable
soen
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP),
U N I T S S U M M A R Y
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
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