31386
33000
30000
27000
24000
21000
18000
15000
12000
9000
P E R F O R M A N C E
The following tables give a survey about the
Core area and performance in Programmable
Logic Devices after Place & Route (CPU fea-
tures and peripherals have been included):
Device
FLEX10KE
ACEX1K
APEX20K
APEX20KE
APEX20KC
APEX-II
MERCURY
CYCLONE
CYCLONE-II
STRATIX
Speed grade
Fmax
-1
-1
-1
-1
-7
-7
-5
-6
-6
-5
-3
50 MHz
50 MHz
45 MHz
55 MHz
66 MHz
72 MHz
95 MHz
85 MHz
91 MHz
92 MHz
154 MHz
6000
3000
1550
268
0
80C51 (12MHz)
DP80390XP (150MHz)
80C310 (33MHz)
Area utilized by the each unit of DP80390XP
core in vendor specific technologies is summa-
rized in table below.
STRATIX-II
Core performance in ALTERA® devices
Area
Component
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and theirs improvement
are shown in table below. Improvement was
computed as {80C51 clock periods} divided by
{DP80390XP clock periods} required to exe-
cute an identical function. More details are
available in core documentation.
[LC]
1790
50
40
40
30
20
150
100
10
[FFs]
315
32
0
0
8
10
40
25
5
35
50
60
60
60
120
70
55
60
45
CPU*
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR0 & DPTR1 auto-switch
Timed Access protection
Interrupt Controller
INT2-INT6
Power Management Unit
I/O ports
100
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
Improvement
9,00
Timers
Timer 2
UART0
UART1
160
170
210
210
260
160
110
150
100
500
9,00
9,00
12,00
9,00
9,00
Master I2C Unit
Slave I2C Unit
SPI Unit
Compare Capture Unit
Watchdog Timer
Multiply Divide Unit
9,00
12,00
16,00
9,60
105
1155
8-bit division
Total area
4360
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
12,00
12,00
13,60
12,00
12,00
12,60
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization in all technologies except
STRATIX-II
Average speed improvement:
11,12
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DP80390XP per-
formance in terms of Dhrystone/sec and VAX
MIPS rating.
Clock
fre-
quency
12 MHz
33 MHz
Dhry/sec
(VAX MIPS)
Device
Target
80C51
80C310
-
-
268 (0.153)
1550 (0.882)
31386 (17.85)
DP80390XP STRATIX-II 150 MHz
Core performance in terms of Dhrystones
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