○ FADD, FSUB - addition, subtraction
○ FMUL, FDIV- multiplication, division
○ FSQRT- square root
- used
- unused
• DoCD™ debug unit
○ FUCOM - compare
○ FCHS - change sign
○ FABS - absolute value
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
● Floating-Point math coprocessor - IEEE-
754 standard single precision real, word
and short integers
D E L I V E R A B L E S
♦ Source code:
○ FADD, FSUB- addition, subtraction
○ FMUL, FDIV- multiplication, division
○ FSQRT- square root
○ FUCOM- compare
○ FCHS - change sign
○ FABS - absolute value
○ FSIN, FCOS- sine, cosine
○ FTAN, FATAN- tangent, arcs tangent
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
C O N F I G U R A T I O N
The following parameters of the DP80390XP
core can be easy adjusted to requirements of
dedicated application and technology. Configu-
ration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
Delivery the IP Core updates, minor and
major versions changes
Internal Program Memory
type
- synchronous
- asynchronous
•
•
•
•
•
•
•
•
•
•
•
•
●
●
Delivery the documentation updates
Phone & email support
Internal Program ROM
Memory size
-
0 - 64kB
-
L I C E N S I N G
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Internal Program RAM
Memory size
-
0 - 64kB
-
Internal Program Memory
fixed size
- true
- false
Second Data Pointer
(DPTR1)
- used
- unused
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implementa-
tion. It also permits FPGA prototyping before
ASIC production.
- used
- unused
DPTR0 decrement
DPTR1 decrement
Data Pointers auto-switch
Interrupts
Unlimited Designs license allows using IP Core
in unlimited number of FPGA bitstreams and
ASIC implementations.
- used
- unused
- used
- unused
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
subroutines
location
-
- used
- unused
Timing access protection
Power Management Mode
Stop mode
● Single Design license for
○ VHDL, Verilog source code called HDL Sour-
ce
- used
- unused
○ Encrypted, or plain text EDIF called Netlist
- used
- unused
● Unlimited Designs license for
○ HDL Source
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
