B L O C K D I A G R A M
P I N S D E S C R I P T I O N
PIN
TYPE
DESCRIPTION
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
Opcode
clk
input Global clock
input Global reset
input Port 0 input
input Port 1 input
input Port 2 input
input Port 3 input
I/O Port
decoder
registers
reset
prgramdata(7:0)
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
Program
memory
interface
t0
t1
gate0
gate1
Timers
UART
xramaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xramdataz
ready
iprgramsize[2:0] input Size of on-chip RAM CODE
iprgromsize[2:0] input Size of on-chip ROM CODE
prgramdata[7:0] input Data bus from int. RAM prog. memory
prgromdata[7:0] input Data bus from int. ROM prog. memory
rxdi
rxdo
txd
External
memory
interface
xprgrd
xprgwr
xdatard
xdatawr
int0
int1
int2
int3
int4
int5
int6
sxdmdatai[7:0]
input Data bus from sync external data
memory (SXDM)
Interrupt
controller
xdatai[7:0]
ready
ramdatai[7:0]
sfrdatai[7:0]
int0
input Data bus from external memories
input External memory data ready
input Data bus from internal data memory
input Data bus from user SFR’s
input External interrupt 0
input External interrupt 1
input External interrupt 2
input External interrupt 3
input External interrupt 4
input External interrupt 5
input External interrupt 6
input Timer 0 input
Control
Unit
iprgromsize(2:0)
iprgramsize(2:0)
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
Power
Manage-
ment Unit
stop
Internal data
memory
interface
int1
pmm
ramoe
int2
int3
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
tdi
tck
User SFR’s
interface
int4
tms
DoCD™
Debug Unit
tdo
int5
rtck
sfrwe
coderun
int6
debugacs
t0
Floating
Point Unit
t1
input Timer 1 input
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
SXDM
interface
t2
input Timer 2 input
gate0
gate1
t2ex
input Timer 0 gate input
input Timer 1 gate input
input Timer 2 gate input
input Timer 2 capture 0 line
input Timer 2 capture 1 line
input Timer 2 capture 2 line
input Timer 2 capture 3 line
input Serial receiver input 0
input Serial receiver input 1
input Master/Slave I2C clock line input
input Master/Slave I2C data input
input SPI slave select
sxdmwe
t2
t2ex
Timer 2
Watchdog
Timer
capture0
capture1
capture2
capture3
rxdi0
capture0
capture1
capture2
capture3
Compare
Capture
rxd0o
rxd0i
txd0
UART 0
rxd1o
rxd1i
txd1
rxdi1
UART 1
MDU32
scli
so
si
mo
mi
scko
scki
scken
ss
sso(7:0)
soen
sdai
ss
SPI Unit
si
input SPI slave input
mi
input SPI master input
scki
input SPI clock input
sclhs
scli
sclo
sdai
sdao
tdi
input DoCD™ TAP data input
input DoCD™ TAP clock input
input DoCD™ TAP mode select input
output Reset output
Master/
Slave I2C
Unit
tck
ALU
tms
clk
reset
rsto
rsto
port0o[7:0]
port1o[7:0]
port2o[7:0]
output Port 0 output
output Port 1 output
output Port 2 output
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
