SRAM or FLASH device. Because of relatively
long access time the program code executed
from mentioned above devices must be
fetched with additional Wait-States. Number of
required Wait-States depends on memory ac-
cess time and DP80390XP clock frequency. In
most cases the proper number of Wait-States
cycles is between 2-5. The READY pin can be
also dynamically modulated e.g. by SDRAM
controller.
other applications whole program code can be
implemented as off-chip ROM or FLASH and
executed with required number Wait-State cy-
cles.
0x7FFFFF
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x00FFFF
On chip Memory
(implemented as RAM)
0x00F000
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x000400
On-chip Memory
(implemented as ROM)
0x000000
The figure below shows a typical Program
Memories connections in system with
DP80390XP Microcontroller core.
8
prgramdatai
8
On-chip Memory
(implemented as RAM)
0 Wait-State access
prgdatao
prgramwr
12
10
prgaddr
On-chip Memory
(implemented as ROM)
0 Wait-State access
8
prgromdata
ASIC or FPGA
chip
DP80390XP
xdatai
xdatao
xaddr
8
Off-chip Memory
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
24
xprgrd
xprgwr
Wait-States
manager
ready
The described above implementation should be
treated as an example. All Program Memory
spaces are fully configurable. For timing-critical
applications whole program code can be imple-
mented as on-chip ROM and (or) RAM and
executed without Wait-States, but for some
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