DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
1.1
1.0
Jabber detect
0, RO/LH Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a DM9010BI reset. This bit works only in
10Mbps mode
Extended Capability
1 = Extended register capable
Extended
capability
1,RO/P
0 = Basic register capable only
8.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9010BI. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a
model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
Description
2.15-2.0
OUI_MSB
<0181h>
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) - 03
Bit
Bit Name
Default
Description
3.15-3.10
OUI_LSB
<101110>, OUI Least Significant Bits
RO/P
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
3.9-3.4
3.3-3.0
VNDR_MDL
MDL_REV
<001011>, Vendor Model Number
RO/P
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
<0000>,
RO/P
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 4)
8.5 Auto-negotiation Advertisement Register (ANAR) - 04
This register contains the advertised abilities of this DM9010BI device as they will be transmitted to its link partner
during Auto-negotiation.
Bit
Bit Name
Default
Description
4.15
NP
0,RO/P
Next page Indication
0 = No next page available
1 = Next page available
The DM9010BI has no next page, so this bit is permanently set to 0
4.14
ACK
0,RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9010BI's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit.
Preliminary
33
Version: DM9010BI--DS-P01
January 12, 2010
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
