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DM9010BI 参数 Datasheet PDF下载

DM9010BI图片预览
型号: DM9010BI
PDF下载: 下载PDF文件 查看货源
内容描述: 工业温度10/100 Mbps的单芯片以太网控制器,带有通用处理器接口 [Industrial-temperature 10/100 Mbps Single Chip Ethernet Controller With General Processor Interface]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 60 页 / 448 K
品牌: DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
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DM9010BI  
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface  
8. MII REGISTER DESCRIPTION  
ADD Name  
00 CONTR Reset  
15  
14  
Loop  
back  
0
13  
12  
11  
10  
9
8
Full  
7
6
5
4
3
2
1
0
Speed Auto-N Power Isolate Restart  
select  
1
Coll.  
Test  
0
Reserved  
OL  
Enable Down  
1
Auto-N Duplex  
0
0
0
0
0
1
000_0000  
01 STATUS T4  
TX FDX TX HDX 10 FDX 10 HDX  
Cap.  
1
0
Reserved  
Pream. Auto-N Remote Auto-N  
Supr.  
1
0
Link  
Status  
0
Jabber  
Detect  
0
Extd  
Cap.  
1
Cap.  
0
0
Cap.  
1
0
Cap.  
1
0
Cap.  
1
0
Compl.  
0
0
Fault  
0
0
Cap.  
1
0
0000  
02 PHYID1  
03 PHYID2  
0
1
1
0
0
1
OUI_LSB  
101110  
04 Auto-Neg. Next FLP Rcv Remote  
Model No.  
01010  
TX FDX TX HDX 10 FDX 10 HDX  
Adv  
LP  
Version No.  
0000  
Reserved  
FC  
Adv  
LP  
T4  
Adv  
LP  
Advertised Protocol Selector Field  
Advertise Page  
05 Link Part. LP  
Ack  
LP  
Fault  
LP  
Adv  
LP  
Adv  
LP  
Adv  
LP  
Reserved  
Link Partner Protocol Selector Field  
Ability  
Next  
Ack  
RF  
FC  
T4  
TX FDX TX HDX 10 FDX 10 HDX  
Page  
06 Auto-Neg.  
Reserved  
TX  
Pardet LP Next Next Pg New Pg LP AutoN  
Expansio  
n
16 Specifie BP  
Fault  
Pg Able  
Able  
Rcv  
Cap.  
BP  
SCR  
BP  
ALIGN  
BP_ADP Reserve  
Reserve Reserve Force Reserve Reserve RPDCTR Reset  
100LNK -EN St. Mch  
Pream.  
Supr.  
Sleep  
mode  
Remote  
LoopOut  
d
4B5B  
OK  
dr  
d
d
d
d
Config.  
17 Specifie 100  
100  
10  
10 HDX Reserve Reverse Reverse  
PHY ADDR [4:0]  
Auto-N. Monitor Bit [3:0]  
d
FDX  
HDX  
FDX  
d
d
d
Conf/Stat  
18  
10T  
Conf/Stat  
Rsvd  
LP  
Enable  
HBE  
SQUE  
JAB  
Reserve  
d
Reserved  
Polarity  
Reverse  
Enable Enable Enable  
19 PWDOR  
Reserved  
PD10DR PD100l PDchip PDcrm PDaeq PDdrv  
V
PDecli PDeclo PD10  
20 Specified TSTSE1 TSTSE2 FORCE_ FORCE_  
Reserved  
MDIX_C AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Reserve PD_valu  
NTL _dlpbk Value wn  
config  
TXSD  
FEF  
d
e
Key to Default  
In the register description that follows, the default  
column takes the form:  
<Reset Value>, <Access Type> / <Attribute(s)>  
<Access Type>:  
RO = Read only  
RW = Read/Write  
<Attribute (s)>:  
Where:  
SC = Self clearing  
<Reset Value>:  
P = Value permanently set  
LL = Latching low  
LH = Latching high  
1
0
X
Bit set to logic one  
Bit set to logic zero  
No default value  
Preliminary  
30  
Version: DM9010BI--DS-P01  
January 12, 2010  
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