DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
0 = Normal operation
16.12
BP_ADPOK
0, RW
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug only,
not release to customer
1=Forced SD is OK,
0=Normal operation
16.11
16.10
Reserved
TX
RW
Reserved
Force to 0 in application
100BASE-TX Mode Control
1 = 100BASE-TX operation
Reserved
1, RW
16.9
16.8
Reserved
Reserved
0, RO
0, RW
Reserved
Force to 0 in application.
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
16.7
F_LINK_100
0, RW
16.6
Reserved
0, RW
Reserved
Force to 0 in application.
Reserved
Force to 0 in application.
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
16.5
16.4
Reserved
0, RW
1, RW
RPDCTR-EN
1 = Enable automatic reduced power down
Reset State Machine
16.3
16.2
SMRST
MFPSC
0, RW
1, RW
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
16.1
SLEEP
0, RW
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loop out Control
16.0
RLOUT
0, RW
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Preliminary
36
Version: DM9010BI--DS-P01
January 12, 2010
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
