DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.50 Interrupt Status Register (FEH)
Bit
Name
Default
Description
7:6
IOMODE
T0, RO
Bit 7 Bit 6
0
0
1
1
0
1
0
1
16-bit mode
32-bit mode
8-bit mode
Reserved
5
4
3
2
1
0
LNKCHG
UDRUN
ROO
ROS
PHS0,RW/C1 Link Status Change
PHS0,RW/C1 Transmit Under run
PHS0,RW/C1 Receive Overflow Counter Overflow
PHS0,RW/C1 Receive Overflow
PHS0,RW/C1 Packet Transmitted
PHS0,RW/C1 Packet Received
PT
PR
6.51 Interrupt Mask Register (FFH)
Bit
7
Name
PAR
Default
HPS0,RW
Description
Enable the SRAM read/write pointer to automatically return to the start address
when pointer addresses are over the SRAM size. Driver needs to set. When
driver sets this bit, REG_F5 will set to 0Ch automatically
Reserved
Enable Link Status Change Interrupt
Enable Transmit Under run Interrupt
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
6
5
4
3
2
1
0
RESERVED
LNKCHGI
UDRUNI
ROOI
RO
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
ROI
PTI
PRI
Enable Packet Received Interrupt
Preliminary
28
Version: DM9010BI--DS-P01
January 12, 2010
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
