DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.37 INT Pin Control Register (39H)
Bit
Name
Default
Description
7:2
Reserved
PS0,RO
Reserved
INT Pin Output Type Control
1
0
INT_TYPE
INT_POL
PET0,RW 1: INT Open-Collector output
0: INT direct output
INT Pin Polarity Control
PET0,RW 1: INT active low
0: INT active high
6.38 Monitor Register 1 (40H)
Bit
7
6
5
4
Name
BWIDTH
DWIDTH
INTOC
INTP
Default
T0,RO
T0,RO
Description
8-bit Data Strap Latch Status
32-bit Data Strap Latch Status
ET0,RO INT Open-Collect Pin Status
ET0,RO INT Polarity Pin Status
3
2
IO16OC
IO16P
E0,RO
E0,RO
IO16/32 Open-Collect Pin Status
IO16/32 Polarity Pin Status
1
0
ILEDM
MDIX
ET0,RO LED Mode Status
ET0,RO MDIX Strap Pin Status
6.39 Monitor Register 2 (41H)
Bit
7~4
3
2
1
Name
RESERVED
NOEEP
EXTMII
PHYUP
RMII
Default
0,RO
T0,RO
T0,RO
T0,RO
T0,RO
Description
Reserved
NO Load EEPROM Strap Pin Status
External MII Strap Pin Status
PHY Power-Up Strap Pin Status
Reverse MII strap Pin Status
0
6.40 System Clock Turn ON Control Register (50H)
Bit
Name
Default
Description
7:1
Reserved
-
Reserved
Stop Internal System Clock
0
DIS_CLK
P0,W
1: internal system clock turn off, internal PHYceiver also power down
0: internal system clock is ON
6.41 Resume System Clock Control Register (51H)
When the INDEX port set to 51H, the internal system clock is turn ON.
6.42 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
7:0
MRCMDX
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged. And the DM9010BI starts to pre-fetch the SRAM data
to internal data buffers.
Preliminary
26
Version: DM9010BI--DS-P01
January 12, 2010
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
