DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
PH0,RW Retry Late Collision Packet
Re-transmit the packet with late-collision
PH0,RW Disable TX Under run Retry
Disable to re-transmit the underruned packet
PH0,RW One Packet Mode
6
5
4
RLCP
DTU
ONEPM
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
3~0
IFGS
PH0,RW Inter-Frame Gap Setting
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010:80-bit
1011:88-bit
1100:96-bit
1101:104-bit
1110: 112-bit
1111:120-bit
6.26 Operation Test Control Register (2EH)
Bit
Name
Default
Description
7~6
SCC
PH0,RW System Clock Control
Set the internal system clock.
00: 50Mhz
01: 20MHz
10: 100MHz
11: 1KHz
In external MII mode, only internal system clock is always 50Mhz.
5
4
3
EXTMII
SOE
SCS
PH0,RW Force to External MII mode
PH0,RW SRAM Output-Enable Always ON
PH0,RW SRAM Chip-Select Always ON
PH0,RW PHY operation mode
2~0
PHYOP
6.27 Special Mode Control Register (2FH)
Bit
7
Name
SM_EN
Default
Description
HPS0,RW Special Mode Enable
6~3
2
1
RESERVED HPS0,RO Reserved
FLC
FB1
FB0
HPS0,RW Force Late Collision
HPS0,RW Force Longest Back-off time
HPS0,RW Force Shortest Back-off time
0
6.28 Early Transmit Control/Status Register (30H)
Bit
Name
Default
Description
7
ETE
HPS0, RW Early Transmit Enable
Enable bits[1:0]
Preliminary
23
Version: DM9010BI--DS-P01
January 12, 2010
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
