DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.9 Back Pressure Threshold Register (08H)
Bit
7:4
Name
BPHW
Default
PHS3,
RW
Description
Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
when RX SRAM free space is lower than this threshold value
Default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
:0
JPT
PHS7,
RW
Jam Pattern Time. Default is 200us
bit3 bit2 bit1 bit0
time
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5us
10us
15us
25us
50us
100us
150us
200us
250us
300us
350us
400us
450us
500us
550us
600us
6.10 Flow Control Threshold Register (09H)
Bit
7:4
Name
HWOT
Default
PHS3,
RW
Description
RX FIFO High Water Overflow Threshold
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its means no free RX SRAM space.
Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)
RX FIFO Low Water Overflow Threshold
Send a pause packet with pause time=0000 when RX SRAM free space is larger
than this value. This pause packet is enabled after the high water pause packet is
transmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM
size
3:0
LWOT
PHS8,
RW
(1 unit=1K bytes)
6.11 RX/TX Flow Control Register (0AH)
Bit
Name
Default
Description
7
TXP0
HPS0,RW TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
6
5
TXPF
HPS0,RW TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
HPS0,RW Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
TXPEN
Preliminary
19
Version: DM9010BI--DS-P01
January 12, 2010
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
