64
8Bit Single Chip Microcontroller
DMC73C168
The transmitter and receiver process each data at the same bit position during the same SCLK1
(SCLK2), so an INT5 (INT7) interrupt by the transmitter is generated at the same time an INT5
(INT7) interrupt by the receiver.
SHIFT CLOCK
SCLK Source
INTERNAL SCLK
Fosc
EXTERNAL SCLK
E2 (SCLK1), E5 (SCLK2)
Fosc/8 Max
Band Rate
Fosc/8, Fosc/16, Fosc/32, Fosc/64
SCLK1, 2 Output or I/O Port
E2:SCLK1,E5:SCLK2
Character Length
Error Detection
SCLK1, 2 Input
8bit fixed length
Overrun
Table 5-9. SI/O Feature
(Fosc : Xtal Oscillation Frequency)
* 1 SCLK1E (P27,2)
0 : E2 Normal I/O
1 : - P41.2 = 0 : E2 External SCLK1 input
- P41.2 = 1 : E2 Internal SCLK1 output
SCLK2E (P29,2)
0 : E5 Normal I/O
1 : - P41.5 = 0 : E5 External SCLK1 input
- P41.5 = 1 : E5 Internal SCLK1 output
* 2 SO1ENA (P27.1)
0 : E0 Normal I/O
1 : E0 Serial data output SO1 (P41, 0 = 1)
SO2ENA (P29.1)
P28
SIO1AF
I
N
T
E
R
N
A
L
SI1 SHIFT
KEY
E1 / SI1 PIN
EDATA Reg
EDATA Reg
shift clock
E2 / SCLK1 PIN
SCLK2E *1 (P27.2)
SO1 SHIFT
KEY
E3/SO2 PIN
B
U
S
SO2ENA *2 (P27.1)
P28
SIO1ST
Figure 5-9A. Serial I/O 1 Block Diagram
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