SL811HS
Master/Slave
Controller
INTERRUPT
INTR
CONTROLLER
RAM
SERIAL
INTERFACE
ENGINE
D+
D-
BUFFERS
USB
&
Root-HUB
XCVRS
CONTROL
REGISTERS
nWR
nRD
nCS
PROCESSOR
INTERFACE
CLOCK
GENERATOR
nRST
D0-7
X1
X2
Figure 4-1. SL811HS USB Host/Slave Controller Functional Block Diagram
4.2
SL811HS Host or Slave Mode Selection [Master/Slave Mode]
SL811HS can work in two modes—host or slave. For slave-mode operation and specification, please refer to the SL811S
specification. This data sheet only covers host-mode operation.
4.3
Features
• The only USB Host/Slave controller for embedded systems in the market with a standard microprocessor bus interface.
• Supports both full-speed (12 Mbps) and low-speed (1.5 Mbps) USB transfer
4.3.1
USB Specification Compliance
• Conforms to USB Specification 1.1
4.3.2
CPU Interface
• Operates as a single USB host or slave under software control
• Low-speed 1.5 Mbps, and full speed 12 Mbps, in both master and slave modes
• Automatic detection of either low- or full-speed devices
• 8-bit bidirectional data, port I/O (DMA supported in slave mode)
• On-chip SIE and USB transceivers
• On-chip single root HUB support
• 256-byte internal SRAM buffer, ping-pong operation
• Operates from 12- or 48-MHz crystal or oscillator (built-in DPLL)
• 5 V-tolerant interface
• Suspend/resume, wake up, and low-power modes are supported
• Auto-generation of SOF and CRC5/16
• Auto-address increment mode, saves memory Read/Write cycles
• Development kit including source code drivers is available
• Backward-compatible with SL11H, both pin and functionality
• 3.3V power source, 0.35 micron CMOS technology
• Available in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC).
Document #: 38-08008 Rev. *A
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